1. Field of the Invention
This invention relates to a logic operation unit (LU) adapted for use in a computer system, more particularly, a bit field logic operation unit which performs a logic operation accompanied by a masking operation of a part of an operand.
2. Description of the Related Art
In a computer system, a logic operation such as AND, OR, EOR and the like accompanied by a masking operation is sometimes required. A bit or bits to be masked are specified by mask information, A bit or bits of an operand in the specified bit position are not altered by the logic operation, and only a remaining bit or bits are altered by the logic operation.
This kind of operation can be performed by carrying out the following three processes:
1) logic operation of two operands, PA1 2) calculation of a bit mask pattern from the mask information, and PA1 3) selection of each bit from either a result of the logic operation or one of two operands according to the bit mask pattern.
Conventionally, the logic operation accompanied by the mark operation is realized by controlling an ALU (Arithmetic Logic Unit) provided in the computer system according to a microprogram which is constituted from three microinstructions which correspond to these three processes 1) to 3), respectively.
In the aforementioned manner, however, the logic operation cannot be performed within one machine cycle, because the processes 1) to 3) must be sequentially executed. Therefore, considerable execution time has been required to execute an instruction for manipulating a specified bit or bits. Particularly, in the case where a variable-length bit field is manipulated, many microprogram steps have been required so that a plurality of machine cycles have been occupied.
Another matter to be considered in the design of a logic operation unit is that the number of elements constituting the logic unit and power consumption thereof should be as small as possible.